A CCD solid state imaging device useful as an area sensor, etc. has photoelectric conversion sections, such as photodiodes, and charge transfer sections having charge transfer electrodes for transferring signal charges from the photoelectric conversion sections. The charge transfer electrodes are arranged on charge transfer paths formed in a semiconductor substrate and driven by successive voltage application.
In recent years, the pixel count of solid state imaging devices has been increasing to giga pixels or even greater. With an increase of pixels, it is required to transfer signal charges at a higher speed, i.e., to drive charge transfer electrodes by higher speed pulses. To meet the requirement, reduction of interelectrode distance, i.e., formation of an interelectrode insulating film (an insulating film formed between adjacent charge transfer electrodes) with a reduced width at high precision as well as reduction of charge transfer electrode resistance has been highly demanded.
In the manufacture of solid state imaging devices having single-layered charge transfer electrodes, the charge transfer sections and the photoelectric conversion sections have conventionally been formed simultaneously. According to this method, an electrode material layer is formed on a semiconductor substrate via a gate oxide film, and the electrode material layer is patterned to form charge transfer electrodes with gaps therebetween and to make openings as photoelectric conversion sections simultaneously. Thereafter, the inner walls of the gaps and the surface of the photoelectric conversion sections are thermally oxidized to form a silicon oxide film (see JP-A-2001-352049).
For example, as shown in FIG. 9A, a silicon oxide film 2a having a thickness of 15 nm, a silicon nitride film 2b having a thickness of 50 nm, and a silicon oxide film 2c having a thickness of 10 nm are formed in that order on an n-type silicon substrate 1. These three oxide films constitute a three-layered gate oxide film 2. A polycrystalline silicon film 3 is then formed on the gate oxide film 2.
A resist is formed on the polycrystalline silicon film 3. The resist is exposed to light through a mask of prescribed pattern, developed, and rinsed in accordance with a known photolithographic technique to form a resist pattern R1 as shown in FIG. 9B. The resist pattern usually has an opening width of 0.3 to several micrometers.
As shown in FIG. 9C, the polycrystalline silicon film 3 is selectively etched out through the resist pattern R1 as a mask using the silicon nitride film 2b as an etching stopper. An array of electrodes (polycrystalline silicon film units) is thus formed.
Then, the surface of the electrodes, the substrate exposed between the electrodes, and the substrate corresponding to the photoelectric conversion sections are thermally oxidized to form a silicon oxide film 4S as shown in FIG. 10A. It naturally follows that the gap gp between the polycrystalline silicon film units 3, i.e., adjacent electrodes is widened by the two thicknesses of the silicon oxide film 4S.
A silicon nitride film 5 is formed on the silicon oxide film 4S as shown in FIG. 10B. Finally, a pn junction is made in the photoelectric conversion sections by ion implantation to form photodiodes. In this way, there is fabricated a solid state imaging device having single-layered charge transfer electrodes made of the polycrystalline silicon film 3.